1. Field of the Invention
The present invention concerns a semiconductor device and a method of manufacturing a semiconductor device. The present invention can be utilized, for example, for a lateral bipolar transistor and a method of manufacturing the same. In particular, the present invention can be utilized as a lateral bipolar transistor of an SOI structure and a method of manufacturing the same.
2. Description of the Related Art
A bipolar transistor of an SOI structure has been proposed with an aim of reducing junction capacitance Cjs, improvement of a-ray resistance or the like.
On the other hand, as a structure for improving the operation characteristics of a bipolar transistor, a vertical bipolar transistor capable of easily reducing the width of a base has been proposed.
In the vertical bipolar transistor, a buried layer is generally formed in order to reduce parasitic resistance. However, in a case of forming the buried layer, since the area for forming the bipolar transistor is increased, high density integration becomes difficult.
In view of the above, a lateral bipolar transistor of an SOI structure capable of easily reducing the width of a base has been proposed.
There are many proposals for semiconductor devices of the SOI structure and there are also various means for forming them. Any of the means can be used when the present invention is applied to the SOI structure and, as one of such forming methods, a method referred to as a method of forming a bonded SOI structure has been known. Description will now be made for the formation of the SOI structure referring to the above-mentioned method as an example with reference to FIG. 3. ("Low Leakage SOIMOSFETs Fabricated Using a Wafer Bonding Method", M. Hashimoto et. al., Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp 89-92).
As shown in FIG. 1-A, a surface on one side of a silicon substrate 1 (a highly flattened silicon wafer is generally used and it is hereinafter referred to as a substrate A) is patterned by using photolithography or etching technology, to form a recess of a depth of 1,500 A or less.
Then, an insulating portion 2 is formed by forming an SiO.sub.2 film on the surface by means of CVD or the like. Thus, a structure as shown in FIG. 1-B in which the insulating portion 2 is formed on one side of the silicon substrate 1 is obtained. The insulating portion 2 is formed as film having an evenness as shown in the figure conforming the surface shape of the patterned silicon substrate 1.
Further, a poly Si film or the like as a bonded layer 3 is formed to about 5 u thickness on the insulating portion 2 by means of CVD or the like (refer to FIG. 1-C).
The poly Si film as the bonding layer 3 is disposed for forming a highly smooth bonding surface upon appending another substrate in a subsequent step (substrate 4 shown at B in FIG. 1-E).
Then, the surface of the bonding layer 3 is flattened by polishing to form a highly smooth surface (FIG. 1-D). In this case, the bonding layer (polysilicon film) is reduced to a thickness of 3 u or less as a remaining film.
Another substrate 4 (hereinafter referred to as a substrate B) is closely bonded to the polished surface of the bonding layer 3. Both of the surfaces are joined by the close press bonding to obtain a joined structure as shown in FIG. 1-E. Generally, it is said that a firm joining is attained by hydrogen bonds under the effect of water or hydroxy groups interposed between both of the surfaces. Then, usually bonded thermally by heating to attain an extremely firm bonding. The bonding strength is generally greater than 200 kg/cm.sup.2 or greater and, depending on the case as great as 2,000 kg/cm.sup.2. As another substrate 4 to be bonded (substrate b), a silicon substrate like that the substrate 1 (substrate A) is generally used. Since a heating step is often applied after bonding, disadvantage may possibly be caused unless physical properties such as heat expansion coefficient are equal between them. Without such a problem, for example, in a case of prior art shown in FIG. 1 in which another substrate 4 functions merely as a support base, this substrate may not necessarily be a silicon substrate. However, in a case where a device is formed also on another substrate 4 (substrate B) to be bonded, it is required to be a semiconductor substrate capable of forming the device.
Then, the substrate 1 is polished such that the silicon portion of the substrate 1 is reduced to a thickness of about 5 um or less as the remaining film to obtain a structure as shown in FIG. 1-F. In FIG. 1-F, the vertical relationship is reversed with respect to FIG. 1-E, because the vertical relationship is upturned to put the substrate 1 on the upper side in order for the polishing or the subsequent selective polishing. Then, subsequent polishing is applied. In this case, precision finish polishing is applied till the insulating portion 2 is just exposed. Then, a structure as shown in FIG. 1-G, in which the insulating portion 2 having unevenness is surrounded, and a silicon portion 10 is present on the insulating portion 2 is obtained. The silicon portion 10 forms an SOI film. For the structure in which the silicon portion 10 is present on the insulating portion 2 (SOI structure), each of the devices is formed on the silicon portion 10. As shown in FIG. 1-G, since each of the silicon portions 10 is surrounded with the insulating portion 2 a complete device isolation is attained in already from the beginning this constitution.
Description will then be made to a case of forming a lateral bipolar transistor while utilizing various kinds of SOI structures to be formed by the method as described above. That is, a lateral bipolar transistor of a known SOI structure will be described below with reference to FIG. 2. FIG. 2-A is a schematic constitutional plan view, and FIG. 2-B is a schematic constitutional cross sectional view corresponding to a cross section taken along line III--IlI in FIG. 2-A.
As shown in FIG. 2-B, a transistor forming region constituted with a semiconductor portion 13 made of single crystal silicon is disposed on an insulating portion (for example, an insulating substrate such as a silicon oxide substrate) 12 as shown in FIG. 2-B.
In the transistor forming region, there are disposed an emitter region 13, a base region 21, a collector region 20, and a high concentration impurity diffusion layer (portion n.sup.+ to the left of the figure) for forming a collector contact. The collector region 20 is formed with the transistor forming region.
Further, on the transistor forming region, a base take out electrode 17 connected, by way of a silicon oxide film 22, to the base region 21 is formed as shown in FIG. 2-A and FIG. 2-B, and the base take out electrode 17 comprises a laminate structure of polysilicon 16, and an oxide silicon film 22 and polysilicon side walls 15, 18 formed on the sides of the laminate structure. Further, side walls 14, 19 of silicon oxide film are formed on the sides of the base take out electrode, and the base take out electrode 17, an emitter take out electrode (not illustrated) and a collector take out electrode (not illustrated) are separated from each other by the side walls 14, 19.
A lateral bipolar transistor is constituted as described above. In FIG. 2-A, 11, reference numeral 11 represents an external base electrode.
Then, description will now be made to a method of manufacturing the lateral bipolar transistor described above by way of a manufacturing step chart shown in FIG. 3.
As shown in FIG. 3-A, a thin film semiconductor portion 50 made of single crystal silicon is formed on an insulating portion 32 (for example, an insulating substrate which is a silicon oxide substrate) is formed. This can be formed by the SOI structure described previously. The thin film semiconductor portion 50 is introduced with N-impurity.
Subsequently, a silicon oxide film 44 and p.sup.+ poly Si 45 are formed by chemical vapor phase deposition method.
Then, as shown in FIG. 3-B, a laminate film of the p.sup.+ poly Si 45 and the silicon oxide film 44 shown in FIG. 3(a) are fabricated respectively into poly Si 37 and silicon oxide 31. The fabrication width in this case corresponds to a collector length.
As shown in FIG. 3(c) successively, poly Si side walls 38, 41 are formed on the side walls on the side of the emitter by chemical vapor phase deposition and subsequent anisotropic etching. The side walls 38, 41 function as a base contact.
Then, after covering the side of the emitter with a resist, N.sup.+ ions are implanted over the entire surface. This forms a high concentration impurity diffusion region for forming the collector contact.
Successively, silicon oxide side walls 46, 47 are formed on the side walls of the laminate film of the P.sup.+ poly Si 37 and the silicon oxide film 31 by chemical vapor phase deposition and subsequent anisotropic etching. Successively, base ions are implanted over the entire surface. FIG. 3-C shows the cross sectional structure at this instance.
Then, N.sup.+ ions are implanted over the entire surface to form an emitter. Successively, silicon oxide side walls 39, 40 of a relatively large thickness are formed on the side walls of the laminate film of the P.sup.+ poly Si 37 and the silicon oxide film 31 and then silicidation process is applied. The silicide portion is detected by reference numeral 42. Since the side walls 39, 40 function to apart the silicides 43, 48 from the emitter base junction, the thickness has to be by a increased relatively large amount. Thus, a cross sectional structure as shown in FIG. 3-D is obtained. As described above, a lateral bipolar transistor is formed.
However, as can be seen from a 2-dimensional impurity profile of similarily constructed transistor 54 shown in FIG. 4, since the base 51 (adjoining p++ poly Si layer and SOI layer 50) and the emitter 53 are formed by side diffusion from above, scattering is caused in the direction of the depth to the width of the base region 51, formed over semiconductor portion 52.
Specifically, the width of the base region 51 is increased as it is away from the surface to bring about an undesirable effect in this portion such as reduction of current amplification h.sub.PE or lowering of cut-off frequency f.sub.T. This causes scattering of characteristics due to the scattering of the thickness of the SiO silicon film.
Further, in the existent lateral bipolar transistor, since ion implantation is applied by using the side walls 46, 47 of the silicon oxide film as a mask and, subsequently, the base and the emitter are formed by diffusion from above, the width of the base region tends to suffer from the effect of the width of the side walls 46, 47 of the silicon oxide film and it is also regulated by the subsequent heat treatment.
Accordingly, the width of the base region varies depending on the width of the side walls 46, 47 of silicon oxide film and conditions of heat treatment, so that electric characteristics such as current amplification factor h.sub.PE or cut-off frequency f.sub.T vary.
In view of the above, it has been desired to provide a lateral bipolar transistor having a narrow size for the width of the base and having a base region with high dimensional accuracy for the width of the base.
Description will now be made to the second related art.
Bipolar transistors of a SOI structure has now been under development with an aim, for example, of improvement to the low parasitic capacitance, latch-up free and a-ray resistance and FIG. 5 shows a cross sectional view of a bipolar transistor of an SOI structure prepared by the existent method.
In a bipolar transistor shown in FIG. 5, an N-type silicon substrate is bonded on a substrate oxidized over the entire surface (SiO.sub.2) 81 and, after forming a field oxide film 91 and SiO.sub.2 84 by device isolation, a contact hole is opened on a collector region. Then, after forming poly Si and SiO.sub.2 successively over the entire surface of the N-substrate, the poly Si and SiO.sub.2 are removed while leaving poly Si 82 and SiO.sub.2 85 on the collector region. Then, after implanting boron over the entire surface of the N-substrate, a SiN side wall 82 is formed. Then, after covering the base take-out region with a resist pattern, arsenic is ion implanted. In this case, P-ions below the SiN side wall 82 are left and P ions in other regions are compensated by N.sup.+ ions to form an N.sup.+ diffusion layer 89 and a P diffusion layer 87. Then, after patterning the interlayer insulating film 92, aluminum is vapor deposited on the surface of the N-substrate to form an electrode 88. As a result, the N.sup.+ diffusion layer 89 forms an emitter region, the P diffusion layer 87 forms a base region and the N-diffusion layer 83 forms a collector region.
However, according to the method shown in FIG. 5, the base region 87 is formed by using the side wall of the SiN 82 for arsenic ions. Accordingly, the width of the base region is controlled by the width of the side wall. However, since the width of the side wail varies and is difficult to be controlled, control for the width of the base is also difficult to bring about a problem.
Further, since the base take-out region is formed in a direction perpendicular to the direction of the width of the base, a base current flows along a long path and the base resistance is increased by so much to bring about a problem.
Further, in the transistor of the SOI structure, latch-up free and reduced parasitic capacitance can be realized by complete insulator separation.
As one of methods for obtaining the SOI substrate, a method of applying ion implantation of oxygen at an order, for example, of 10.sup.17 cm.sup.-2 (hereinafter sometimes simply referred to as implantation) and subsequent high temperature annealing has been known, because a crystal silicon layer can be formed relatively simply and at a good reproducibility.
More specifically, ion implantation of oxygen is applied, for example, at an order of 10.sup.17 cm.sup.-2 to a silicon semiconductor substrate 91 shown in FIG. 6-A as schematically shown by reference I shown in FIG. 6-B (1on implanted portion is schematically shown at 94) and then annealing is applied at 1250.degree. in an inert gas atmosphere in a diffusion furnace to obtain an SiO.sub.2 film as an insulating film 92 and then crystal silicon film 93 is formed thereover, to obtain a structure shown in FIG. 6-C.
In the known technique as described above, annealing in a diffusion furnace at a temperature of about 1,250.degree. C. for several hours is used as a heat treatment after oxygen implantation. The high temperature annealing is applied for sharpening making a dull side slope of an oxygen distribution in implantation abrupt by depositing or out diffusing oxygen from the surface and further, recovering defects caused by high dose implantation, thereby forming a crystal silicon layer and oxide layer. However, since the annealing is applied at high temperature, defects such as slip lines are liable to be caused to bring about a problem for practical use. In addition even annealing at about 1250.degree. C. is still insufficient for the recovery of defects caused by implantation at the order of 10.sup.17 cm.sup.-2. Further, since a high temperature heat treatment is inevitably used for forming the SiO layer in this method, it is difficult to obtain a multi-layered SOI substrate.